The present invention relates to a semiconductor device, and particularly to a semiconductor device which performs a verify operation on stored data.
A semiconductor device, for example, a flash memory capable of storing information in a floating gate (FG) by injecting electrons into the floating gate or extracting the same therefrom has been developed. The flash memory includes memory cells each having a floating gate, a control gate (CG), a source, a drain and a well (substrate). In each memory cell, its threshold voltage rises when electrons are injected into the floating gate, whereas it is reduced when the electrons are extracted from the floating gate. In general, a distribution of the lowest threshold voltage is called “erase state of each memory cell”. A distribution of a threshold voltage higher than at the erase state is called “write state of each memory cell”. When, for example, a memory cell stores data of two bits therein, a distribution of the lowest threshold voltage corresponds to a logical level “11”. This state is called “erase state”. By effecting a write operation on each memory cell and making its threshold voltage higher than at the erase state, a threshold voltage corresponding to each of logical levels “10”, “01” and “00” is obtained. This state is called “write state”.
While the flash memory is normally provided with a plurality of memory cells, the threshold voltages of the memory cells vary due to variations in production and the like. Therefore, the flash memory performs a verify operation for supplying a read voltage to a control gate of each memory cell after data writing and data erasure and determining, based on whether the memory cell is brought to an on state or an off state, whether a threshold voltage distribution of the memory cell falls within a desired range (refer to, for example, patent documents 1 (Japanese Unexamined Patent Publication No. 2002-140899), 2 (Japanese Unexamined Patent Publication No. 2004-192780), 3 (Japanese Unexamined Patent Publication No. 2000-163977) and 4 (Japanese Unexamined Patent Publication No. Hei 11 (1999)-242894)).